1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a complementary metal-oxide-semiconductor device (to be simply referred to as a CMOS device hereinafter) capable of preventing an abnormal operation called a latch-up phenomenon.
2. Description of the Prior Art
A CMOS device which constitutes a circuit by connecting p-channel MOSFETs and n-channel MOSFETs in series is a high-speed device with a low current consumption and used as the core device of a MOS semiconductor device. However, in the CMOS device of a single well scheme or double well scheme, a pnpn junction is inevitably formed in the device because of its structure. This device substantially has a serious problem such that this parasitic thyristor may be turned on to set the device in a latch-up state.
FIG. 1 is a sectional view of a general CMOS device. As shown in FIG. 1, an n-channel MOSFET (to be referred to as an nMOS hereinafter) having n.sup.+ impurity regions 2 and 3, a p.sup.+ impurity region 13 for applying a substrate potential, and an n-well 7 are formed in a p-type semiconductor substrate 8. P.sup.+ impurity regions 4 and 5 serving as the source and drain regions of a p-channel MOSFET (to be referred to as a pMOS hereinafter) and an n.sup.+ impurity region 6 for applying a substrate potential to the well are formed in the n-well 7. The p.sup.+ impurity region 4 serving as the drain region of the pMOS and the n.sup.+ impurity region 3 serving as the drain region of the nMOS are commonly connected to an output terminal OUT. The p.sup.+ impurity region 5 serving as the source region of the pMOS and the n.sup.+ impurity region 6 are commonly connected to a high-potential power supply V.sub.DD. The n.sup.+ impurity region 2 serving as the source region of the nMOS and the p.sup.+ impurity region 13 are commonly connected to a low-potential power supply V.sub.SS (ground).
As shown in FIG. 1, a parasitic pnp transistor Q1, a parasitic npn transistor Q2, and parasitic resistances R1 and R2 are formed in this CMOS device. If one of the two parasitic transistors, e.g., the parasitic npn transistor Q2 is turned on due to some reason, the base potential of the parasitic pnp transistor Q1 is lowered. When the emitter-base path of this transistor is forward-biased, the parasitic pnp transistor Q1 is also turned on. A positive feedback loop constituted by the transistors Q1 and Q2 operates to flow a large current between the power supplies V.sub.DD and V.sub.SS With this operation, the device erroneously operates. In the worst case, thermal breakdown occurs.
Japanese Unexamined Patent Publication No. 3-96272 has proposed a technique in which a guard band is formed between the two MOSFETs as a means for preventing the latch-up phenomenon. FIGS. 2A and 2B are sectional and plan views, respectively, of a CMOS device proposed in this prior art. As shown in FIGS. 2A and 2B, a guard band 16 as an n-well is formed between an nMOS region 11 and a pMOS region 12. An n.sup.+ impurity region 15 in this guard band 16 is connected to a power supply V.sub.DD. A p.sup.+ impurity region 14 formed in contact with a p-type semiconductor substrate 8 is connected to a low-potential power supply V.sub.SS.
In the CMOS device having the above structure, a parasitic npn transistor Q2 and a dummy npn transistor Q3 having a base resistance lower than that of the parasitic npn transistor Q2 are connected in parallel with each other. With this structure, the dummy npn transistor Q3 can be turned on prior to the parasitic npn transistor Q2, so that the operation of the positive feedback loop constituted by a parasitic pnp transistor Q1 and the parasitic npn transistor Q2 is suppressed.
As a more reliable latch-up prevention means, a technique of isolating the pMOS with an insulating layer has been proposed in Japanese Unexamined Patent Publication No. 1-61942.
In the conventional CMOS device shown in FIGS. 2A and 2B, guard bands must be formed between all the pMOS regions and nMOS regions, resulting in an increase in chip area. In particular, when a large substrate current flows as in an IC having power elements mounted on the same substrate, the parasitic npn transistor Q2 is subsequently turned on after the dummy npn transistor is turned on. For this reason, it is difficult to prevent the latch-up phenomenon only by the use of the dummy npn transistor.
In the technique proposed in Japanese Unexamined Patent Publication No. 1-61942 in which the MOSFET is enclosed with an insulating layer, since the process becomes complex, and the manufacture process takes a long time, the yield decreases, and the manufacturing cost increases.